The invention resides generally in digital modulation schemes which employ a phase-locked loop. In particular it is directed to new delta-sigma based dual port modulation schemes and calibration techniques applicable to similar modulation schemes wherein gain adjustments must further be calibrated.
In order to support both voice and data communications, data transmission rates in excess of 1 Mb/s are now being commonly employed in wireless communications systems. The modulation of the carrier signal for transmission of such high-rate data streams must be very accurate, in terms of specific modulation index and spectral properties, while having a high spectral purity. It is also desirable that circuits used to generate such waveforms have low power consumption.
Several approaches to digital modulation of the carrier signal are known in the prior art. One approach is to generate the in phase (I) and quadrature (Q) components of the modulation at baseband using a direct digital synthesizer (DDS) and upconverting this to radio frequencies (RF) using frequency translation, i.e., using conversion mixers and RF synthesizers. Disadvantages of this approach are phase and amplitude mismatch in the I and Q paths, high analog complexity, and poor spurious performance.
Another known approach is to directly modulate the voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) while simultaneously opening the loop. Disadvantages of this approach are carrier centre frequency drift (due to lack of feedback which in a closed PLL causes the VCO output signal to be set and locked to this frequency) and inaccurate modulation index due to variations in the tuning gain of the VCO due to process variations, temperature drift, and non-linearity of the tuning curve.
A third known approach is a direct modulation of a PLL within the loop bandwidth, allowing the carrier frequency to be set precisely. The direct modulation can be achieved by modulating the reference signal generator (the reference clock) of the PLL using a DDS or some other form of phase or frequency modulator. This normally results in high power consumption, particularly when using a DDS based modulator, or in inaccurate setting of the modulation index.
Another method of modulating the loop is through fractional-N frequency division. While several possible techniques of achieving fractional frequency division in a PLL exist, delta-sigma techniques provide the spectral purity and resolution required for direct modulation.
See, for example, Norman M. Filiol et al., xe2x80x9cAn Agile ISM Band Frequency Synthesizer with Built-In GMSK Data Modulationxe2x80x9d IEEE Journal of Solid State Circuits, Vol. 33, No. 7, July 1988, pp998-1008; Terrence P. Kenny et al., xe2x80x9cDesign and Realization of a Digital xcex94xcexa3 Modulator for Fractional-n Frequency Synthesisxe2x80x9d IEEE Transactions on Vehicular Technologies, Vol. 48, No. 2, March 1999, pp510-521; Tom A. D. Riley et al., xe2x80x9cDelta-Sigma Modulation in Fractional-N Frequency Synthesisxe2x80x9d, IEEE Journal of Solid State Circuits, Vol. 28, No. 5 May 1993, pp553-559.
For data rates in excess of 100 Kb/s, techniques of direct modulation of a PLL begin to fail, due to the high loop bandwidth required in order to allow the modulation to pass. In order to obtain a stable loop, the loop bandwidth must be a small fraction of the reference frequency (reference clock). For integer-N PLLs, this is difficult to achieve while maintaining a narrow channel spacing with respect to the reference frequency. In fractional-N PLLs, a wider loop bandwidth can be used while maintaining a narrow channel spacing. However, in order to achieve good spectral purity, it is necessary to filter out the high frequency quantization noise in the loop. This is normally achieved through the use of a narrow loop bandwidth relative to the reference frequency and higher order filtering.
U.S. Pat. No. 5,777,521 Jul. 7, 1998 Gillig et al describes a parallel accumulator fractional-N frequency synthesizer in which a xcex94-xcexa3 modulator is used to control the divider in a feedback path of the loop.
Still another approach is digital modulation of the carrier signal is a two-point (or dual port) modulation of a PLL, where one modulation path leads through the VCO and the second through the reference input to the loop. In this approach, the high frequency components of the modulation signal are added directly to the VCO input, whereas the low frequency components are added by modulating the reference signal. A PLL presents a low pass filter response to the signal applied to the reference input, while it presents a high pass filter response to the signal applied to the VCO input. In other words, the transfer function H(w) for the low frequency components of the modulation signal is relatively flat up to the natural or resonant frequency of the PLL. The transfer function for the high frequency components, on the other hand, is represented by 1-H(w) which is relatively flat for frequencies above the resonant frequency. Therefore, by modulating at two points, this scheme can achieve a desirable characteristic of a flat frequency modulation deviation response versus modulation frequency.
The two-point (dual port) modulation also can achieve the above-stated other goals better than other schemes. The main advantage of this approach, however, is that the modulation gain of both modulation paths (high and low frequency) must be known accurately in an absolute sense in order to control the modulation index (and to achieve a flat modulation response). While the low frequency path can often be set to have accurate modulation gain, the high frequency path through the VCO is problematic.
One method of performing this calibration is through the use of a potentiometer which can be adjusted during bench testing to achieve the correct gain. The main disadvantage of this approach is that is must be performed on a part-by-part basis. Also, the potentiometer gain setting will drift over time due to component aging etc.
A second approach is to measure the tuning constant of the VCO and then store this value in an on-chip memory and use this value as an on-chip gain setting. This method has the disadvantage that the gain, again, must be measured on a part-by-part basis. This method, however, does ensure that the gain setting remains accurate over time.
A third approach is to have an on chip analog-to-digital converter (A/D) which measures the VCO tuning voltage for different synthesizer output frequencies. The gain values obtained can then be used to set the gain of the modulation path. This method has the disadvantage that the A/D directly loads the output of the loop filter and for wide bandwidths it needs several bits accuracy in the A/D.
U.S. Pat. No. 4,242,649 Dec. 30, 1980 Washburn, Jr.; U.S. Pat. No. 4,308,508 Dec. 29, 1981 Sommer et al; U.S. Pat. No. 4,313,209 Jan. 26, 1982 Drucker; U.S. Pat. No. 4,543,542 Sep. 24, 1985 Owen; and U.S. Pat. No. 4,743,867 May 10, 1988 Smith provide examples of various such two-point modulation schemes and different calibration techniques including those mentioned above.
U.S. Pat. No. 5,834,987 Nov. 10, 1998 Dent describes a PLL frequency synthesizer with three-point modulation. In this embodiment, a xcex94-xcexa3 modulator is connected to a fractional frequency divider and uses an analog integrator which integrates an error signal until the error signal reaches a threshold defined by a comparator. A flip-flop responds to the output of the comparator and adjusts the fractional frequency divider. Because the accumulated error signal controls the frequency divider, the adjustment tends to be by a large amount, resulting in jitter.
U.S. Pat. No. 5,942,949 Aug. 24, 1999 Wilson et al describes a self calibrating phase-lock loop with auto-trim operations for selecting an appropriate oscillator operating curve. The patent, however, does not describe the calibration of modulation or a modulation technique.
In accordance with one aspect, the present invention provides a new digital frequency modulation scheme which is substantially free of many disadvantages of similar prior art modulation schemes, as outlined above.
In accordance with another aspect, the invention provides a new digital frequency modulation scheme in which modulation gain is accurately calibrated to achieve a flat response to a wide modulation signal. In a further aspect, the invention allows on chip calibration for unknown VCO tuning gain.
It is an object of the present invention to provide a new modulated PLL loop having a dual port modulation.
It is another object of the present invention to provide an improved PLL-type frequency synthesizer having a dual port modulation.
Briefly, the PLL-type modulated frequency synthesizer of the present invention comprises a controlled oscillator whose divided down output frequency is phase locked to the reference frequency of a stable reference oscillator. In a locked loop, the output frequency of the controlled oscillator is a multiple of the reference frequency:
fout=N*fref
where N is known as the division ratio. The frequency division of the controlled oscillator output signal is carried out in the feedback path of the loop by a frequency divider, which can be seen as a single bit phase quantizer allowing 0 or 2xcfx80 radians of phase to be subtracted on each cycle of the divider output. In order to achieve high resolution from a single-bit phase quantizer, a digital xcex94-xcexa3 modulator is used to control the divider. The input to the xcex94-xcexa3 modulator is a digital word which represents the desired output frequency for the synthesizer and the output from the modulator is a bitstream whose average density represents the desired output frequency value plus high pass filtered quantization error.
The output signal of the divider is compared in a phase/frequency detector (PFD) with a stable reference clock signal to produce an error signal related to the difference in a component of the two compared signals. The resulting error signal is processed by a loop filter and used to control the controlled oscillator. This processing also attenuates the high frequency quantization noise introduced into the loop by the xcex94-xcexa3 modulator.
The desired digital modulation signal is applied to the input of the xcex94-xcexa3 modulator. A fixed offset for channel selection is added to these data bits. A fixed offset can be added to the output of the xcex94-xcexa3 modulator as well. As the transfer function from the xcex94-xcexa3 modulator input to the controlled oscillator output is low pass in nature, only low frequency components of the modulating signal are transferred through this path to the controlled oscillator output, when the loop bandwidth is much narrower than the data bandwidth.
In the frequency synthesizer of the present invention, the modulation data bits are also used to modulate directly the controlled oscillator, by summing them with the feedback control signal coming from the loop filter. As the path from the input to the output of the controlled oscillator is high pass in nature, only those frequency components of the modulation signal which fall outside the loop bandwidth appear at the controlled oscillator output. If the scaling factor K of this path is chosen correctly, the overall transfer function (including both paths) from the modulation input to the synthesizer output is all pass in nature and all the frequency components of the modulating signal appear undistorted at the synthesizer output. If the control of spectral properties of modulation is required or desirable, a pulse shaping filter may be inserted in this path (controlled oscillator path) prior to summing with the control signal coming from the loop filter.
In the modulation scheme according to the invention, the xcex94-xcexa3 modulator combined with a digital frequency divider allows an almost perfect control of the low frequency components of the modulating signal. This means that only the gain of the controlled oscillator path needs to be set. The high accuracy of the low frequency path allows calibration to be performed in order to determine the controlled oscillator tuning gain. Finally, the use of delta-sigma modulator to control the frequency divider allows the use of higher reference frequencies and lower division ratios, resulting in a reduced phase noise.